Ingeniero Electrónico DOCENTE CONTRATADO - CONTRATADO Tiempo parcial por asignaturas (TPA) Departamento Académico de Ingeniería - Sección Electricidad y Electrónica
Martins, T.; SALDAÑA, J. C.; Van Noije, W.(2018). A Programmable Gain Amplifier for load demodulation channel in an NFC reader chip. En 2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI). IEEExploreDGITAL.
SALDAÑA, J. C. y Del-Moral-Hernandez, E.(2018). A CMOS Squarer Based Nonlinear Filter for Spike Detection. En 2018 25th IEEE International Conference on Electronics (ICECS). IEEExploreDGITAL.
BEJAR, E. A. M.; SALDAÑA, J. C.; RAYGADA, E. L.; SILVA, C. B.(2017). On the jitter-to-fast-clock-period ratio in oscillator-based true random number generators. En 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS). (pp. 243 - 246). WASHINGTON D. C.. IEEExploreDIGITAL.
SALDAÑA, J. C.; SILVA, C. B.; DEL MORAL, E.(2016). A CMOS Implementation of the Discrete Time Nonlinear Energy Operator Based on a Transconductor-Squarer Circuit. En VII IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS. (pp. 395 - 398). FLORIANOPOLIS. UNIVERSIDAD FEDERAL SANTA CATARINA. Recuperado de: http://gse.ufsc.br/lascas2016/
SALDAÑA, J. C.(2016). A floating voltage regulator with output level sensor for applications with variable high voltage supply in the range of 8.5 V to 35 V. En Micro-Nanoelectronics, Technology and Applications (CAMTA), Argentine Conference of. (pp. 1 - 4). IEEE .
RODRÍGUEZ, L. E.; RAYGADA, E. L.; SILVA, C. B.; SALDAÑA, J. C.(2016). Design of a CMOS cross-coupled voltage doubler. En 2016 IEEE Andescon Andean Council International Conference. (pp. 74 - 77). LIMA. DIGITAL. Recuperado de: www.andescon.org
SALDAÑA, J. C.(2010). Design procedure of a linearized OTA based on GM, THD ans Vos.
SALDAÑA, J. C.(2009). CMOS integrate and fire neuron for temporal logarithmic encoding.
