BEJAR, E. A. M.;
SALDAÑA, J. C.; RAYGADA, E. L.;
SILVA, C. B.(2017).
On the jitter-to-fast-clock-period ratio in oscillator-based true random number generators. En
2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS). (pp. 243 - 246). WASHINGTON D. C.. IEEExploreDIGITAL.
RODRÍGUEZ, L. E.; RAYGADA, E. L.;
SILVA, C. B.;
SALDAÑA, J. C.(2016).
Design of a CMOS cross-coupled voltage doubler. En
2016 IEEE Andescon Andean Council International Conference. (pp. 74 - 77). LIMA. DIGITAL. Recuperado de:
www.andescon.orgSOTO, J. G. M.;
SILVA, C. B.; VILLEGAS, E.(2016).
A Highly Parallel 4K Real-Time HEVC Fractional Motion Estimation Architecture for FPGA Implementation. En
23rd IEEE International Conference on Electronics, Circuits and Systems (ICECS). (pp. 90 - 93). MONTECARLO. DIGITAL. Recuperado de:
http://icecs.isep.fr/SOTO, J. G. M.;
SILVA, C. B.; VILLEGAS, E. C.(2016).
A High Parallel HEVC Fractional Motion Estimation Architecture. En
2016 IEEE Andescon Andean Council International Conference. (pp. 36 - 39). LIMA. DIGITAL. Recuperado de:
www.andescon.orgSALDAÑA, J. C.;
SILVA, C. B.; DEL MORAL, E.(2016).
A CMOS Implementation of the Discrete Time Nonlinear Energy Operator Based on a Transconductor-Squarer Circuit. En
VII IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS. (pp. 395 - 398). FLORIANOPOLIS. UNIVERSIDAD FEDERAL SANTA CATARINA. Recuperado de:
http://gse.ufsc.br/lascas2016/
